WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corp. (NAS: MENT) today announced that it has completed enhancements to its digital tool set for TSMC's 16nm FinFET manufacturing processes. TSMC's ...

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations.

IC Compiler II and Design Compiler Graphical provide a complete digital implementation flow delivering optimized power, performance, area, and full via pillar support StarRC, PrimeTime, NanoTime, and ...

New reference flow offers open, efficient radio frequency design solution that supports streamlined migration from previous process nodes Industry-leading electromagnetic simulation tools boost 5G/6G ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

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As the digital semiconductor manufacturing process moves into the FinFET era, more and more front-end-of-line (FEOL) defects are observed due to extremely small feature size and complex manufacturing ...

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies ...

The company has had it rough for a few years with respect to building its own processing technology but are planning to make a comeback with a new 7nm FinFET process. The interesting thing about the ...