Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.

In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1, we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good ...

This whitepaper gives a compact overview of the recommended gate drive concepts for both GIT (gate injection transistor) and SGT (Schottky gate transistor) product families. A versatile standard drive ...

The research 'Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure' appeared ...

(I also posted this in Other Hardware, 'cause I didn't know where it would get the best response.)<BR><BR>I'm writing a review of some ideas that have been proposed for nano-scale computing ...

While attending APEC 2019, it seemed that gallium-nitride (GaN) transistors were just coming into their own in high-volume applications, while silicon-carbide (SiC) transistors have found wide ...