SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...

Once you have written your model, you are not even half done. Developing tests for your designs can take much more time and more code than the original models. Typical designs require three to ten ...

TestBencher Pro drastically reduces test bench coding and verification time by automatically generating self-checking VHDL and Verilog test benches from graphically entered, reusable timing diagrams.